1. Field
Embodiments discussed herein relate to a semiconductor device and a method for layouting the semiconductor device.
2. Description of Related Art
A semiconductor device includes a logic circuit (random logic) having a specific processing function. The logic circuit includes a cell, and the cell includes an inverter circuit, NAND circuit or NOR circuit which is constituted of a single or a plurality of MOS transistors.
Subsequent to verification of the logic design, the logic circuit is laid out. Based on the laid-out logic circuit, a delay time is calculated, and based on the delay time, the timing is verified. When there is a problem with the timing, a gate size of the MOS transistor, such as a gate length or a gate width of the MOS transistor, is modified or a buffer or the like is inserted to solve the timing problem.
As the gate length of the MOS transistor is increased, the off-leak current decreases. On the contrary, as the gate length of the MOS transistor is shortened, the off-leak current thereof increases. In the logic circuit, the gate length of the MOS transistor included in the cell is increased to reduce the off-leak current, thereby lowering power consumption.
Related art is disclosed in Japanese Laid-open Patent Publication No. H02-218096, Japanese Laid-open Patent Publication No. H02-089365 or the like.